Datasheets
LCMXO2-1200HC-4SG32C

LCMXO2-1200HC-4SG32C

Lattice Semiconductor

Description:

FPGA MachXO2 Family 1280 Cells 65nm Technology 2.5V/3.3V 32-Pin QFN EP Tray

Country of Origin:

Malaysia

Introduction date:

Nov 21, 2000

Updated:10-DEC-2024

See more Field Programmable Gate Arrays - FPGAs by Lattice Semiconductor
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Overview

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LifeCyclePremium
EU RoHS Yes
RoHS Version2011/65/EU, 2015/863
EAR99
Automotive No
Supplier Cage Code66675
8542310060
Schedule B8542310060
PPAP No
AEC Qualified No
Category Path
Semiconductor > Programmable Devices > Programmable Logic Devices > Field Programmable Gate Arrays - FPGAs

Datasheet

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Parametric

The parametric information displays vital features and performance metrics of the component, which helps engineers and supply chain managers to compare and choose the most appropriate electronic component for their applications and needs.

Product Line
Maximum DSP Block Frequency
Maximum MLAB Capacity
Device PCIe Hard IP Blocks
Number of Regional Clocks
Maximum LVDS Data Rate
Maximum Differential I/O Pairs
Maximum I/O Performance
Maximum Distributed RAM Bits
Digital Control Impedance
Number of I/O Banks
Mega Multiply Accumulates per second
Tolerant Configuration Interface Voltage
Minimum Storage Temperature
Number of Inter Dielectric Layers
Maximum Storage Temperature
Shift Registers
Number of Global Clocks
Copy Protection
Typical Supply Current
Maximum Power Dissipation
Temperature Flag
In-System Programmability
Maximum Internal Frequency
Supplier Temperature Grade
Reprogrammability Support
Tradename
Device Logic Gates
Device Logic Units
I/O Voltage
Typical Power Consumption
Maximum Quiescent Current
JTAG Support
Maximum Supply Current
Family Name
Maximum Number of User I/Os
Number of Registers
RAM Bits
Device Logic Cells
Number of Look-up Table Input
Device System Gates
Ethernet MACs
Minimum Operating Supply Voltage
Number of Multipliers
Processor Blocks
Typical Operating Supply Voltage
Transceiver Blocks
Maximum Operating Supply Voltage
Transceiver Speed
Program Memory Type
Dedicated DSP
PCI Blocks
Device Number of DLLs/PLLs
Total Number of Block RAM
Maximum Propagation Delay Time
Giga Multiply Accumulates per Second
Maximum Number of SERDES Channels
Speed Grade
Differential I/O Standards Supported
Single-Ended I/O Standards Supported
External Memory Interface
Supported IP Core
Supported IP Core Manufacture
Minimum Operating Temperature
Maximum Operating Temperature
Programmability
Process Technology

Reference designs

Unlock inspiration and guidance with our collection of reference designs. Explore practical implementations showcasing the capabilities of the electronic component. Accelerate your development process and create efficient solutions with detailed documentation and schematics.

Aptina HiSPi to Parallel Sensor Bridge Reference Design using the LatticeMachXO2-1200 CPLD
Aptina HiSPi to Parallel Sensor Bridge Reference Design using the LatticeMachXO2-1200 CPLD

CAD Models

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