iCE40UP5K-SG48ITR50
Lattice Semiconductor描述: | FPGA iCE40 Ultra Family 5280 Cells 40nm Technology 1.2V 48-Pin QFN EP T/R |
产地: | Malaysia |
推出日期: | Aug 2, 2017 |
更新:10-DEC-2024 | |
在线版本:https://www.datasheets.com/zh-cn/part-details/ice40up5k-sg48itr50-lattice-semiconductor-88053819
概述
熟悉该组件的基本一般信息、属性和特征，以及其与行业标准和法规的符合情况。
生命周期高级
欧盟RoHS Yes
RoHS版本2011/65/EU, 2015/863
EAR99
汽车 No
供应商CAGE代码66675
8542310060
日程B8542310060
PPAP No
AEC认证 No
类别路径
Semiconductor > Programmable Devices > Programmable Logic Devices > Field Programmable Gate Arrays - FPGAs
Semiconductor > Programmable Devices > Programmable Logic Devices > Field Programmable Gate Arrays - FPGAs
技术资料
通过下载该电子元件的数据手册来全面了解其。这个PDF文档包含了所有必要的细节，如产品概述、特性、规格、评级、图表、应用等等。
数据表预览
(Latest 版本)参数
参数信息显示了该组件的重要特性和性能指标，这有助于工程师和供应链经理比较和选择最适合其应用和需求的电子组件。
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生产线
Maximum Distributed RAM Bits
I/O Voltage
Shift Registers
Number of Global Clocks
Copy Protection
Typical Supply Current
Maximum Power Dissipation
Temperature Flag
Supplier Temperature Grade
In-System Programmability
Digital Control Impedance
Number of I/O Banks
Mega Multiply Accumulates per second
Tolerant Configuration Interface Voltage
Minimum Storage Temperature
Number of Inter Dielectric Layers
Maximum Storage Temperature
Maximum DSP Block Frequency
Maximum MLAB Capacity
Device PCIe Hard IP Blocks
Number of Regional Clocks
Maximum LVDS Data Rate
Maximum Differential I/O Pairs
Maximum I/O Performance
Typical Power Consumption
Maximum Quiescent Current
JTAG Support
Maximum Supply Current
Maximum Internal Frequency
Reprogrammability Support
Tradename
Device Logic Gates
Device Logic Units
Family Name
Maximum Number of User I/Os
Number of Registers
RAM Bits
Device Logic Cells
Number of Look-up Table Input
Device System Gates
Ethernet MACs
Minimum Operating Supply Voltage
Number of Multipliers
Typical Operating Supply Voltage
Processor Blocks
Maximum Operating Supply Voltage
Transceiver Blocks
Transceiver Speed
Program Memory Type
Dedicated DSP
PCI Blocks
Device Number of DLLs/PLLs
Total Number of Block RAM
Maximum Propagation Delay Time
Giga Multiply Accumulates per Second
Maximum Number of SERDES Channels
Speed Grade
Differential I/O Standards Supported
Single-Ended I/O Standards Supported
External Memory Interface
Supported IP Core
Supported IP Core Manufacture
Minimum Operating Temperature
Maximum Operating Temperature
Programmability
Process Technology