Programmable Devices

Embedded Systems

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AES Encryption / Decryption cores
pdf
IP Cores
IPX-AES IP Core
Unknown
RapidIO to AXI Bridge Controller (RAB)
pdf
IP Cores
RAB IP Core
Unknown
AHB Master
AHB Master
购买
CAD
pdf
IP Cores
AHB Master IP Core
Unknown
64-Bit PCI Host Bridge
pdf
IP Cores
64-Bit PCI Host Bridge IP Core
Unknown
64-bit PCI Bus Target Interface
pdf
IP Cores
64-bit PCI Bus Target Interface IP Core
Unknown
64-bit PCI Bus Master/Target Interface
pdf
IP Cores
64-bit PCI Bus Master/Target Interface IP Core
Unknown
AHB to PCI Host Bridge
pdf
IP Cores
AHB to PCI Host Bridge IP Core
Unknown
10 Gigabit Fibre Channel FC-1 Core
pdf
IP Cores
10 Gigabit Fiber Channel FC-1 Core IP Core
Unknown
10 Gigabit Ethernet Physical Coding Sublayer (PCS)
pdf
IP Cores
10 Gigabit Ethernet Physical Coding Sublayer IP Core
Unknown
3GPP/LTE CTC Decoder TC7000LTE
pdf
IP Cores
3GPP/LTE CTC Decoder TC7000LTE IP Core
Unknown
40-80 Gbps Transport Switch (TPX4004)
pdf
IP Cores
40-80 Gbps Transport Switch (TPX4004) IP Core
Unknown
6232-01-02
6232-01-02
购买
CAD
pdf
IP Cores
ViClaro II Video Enhancement Board
Unknown
2.5G PDH/SONET/SDH Packet Mapper (TPW48)
pdf
IP Cores
2.5G PDH/SONET/SDH Packet Mapper (TPW48) IP Core
Unknown
AHB Slave
AHB Slave
购买
CAD
pdf
IP Cores
AHB Slave IP Core
Unknown
EF-DI-CTC-80216E-ENC-SITE
pdf
IP Cores
802.16e CTC Encoder v3.0
EF-DI-POSL3PHY-SITE
pdf
IP Cores
The Xilinx® SPI-3 Physical (PHY) Layer core provides a fully compliant Packet over SONET (POS) solution and which can be quickly integrated into networking systems
RIO22000-8-ILT
RIO22000-8-ILT
购买
CAD
pdf
IP Cores
QPRO EXTENDED TEMPERATURE PLATFORM FLASH IN SYSTEM PROGRAMMABLE CONFIGURATION PROM
No
100 Gbps Ethernet MAC
pdf
IP Cores
40- and 100-Gbps Ethernet (40GbE and 100GbE) media access controller (MAC) and PHY Mega Core® functions which implement the IEEE 802.3ba 40G and 100G Ethernet Standard
10GBase-R PHY
10GBase-R PHY
购买
CAD
pdf
IP Cores
The protocol-specific transceiver PHYs configure the PCS to implement a specific protocol. In contrast, the native PHYs provide broad access to the low-level hardware, allowing you to configure many PCS and other functions
40-Gbps Ethernet MAC
pdf
IP Cores
40- and 100-Gbps Ethernet (40GbE and 100GbE) media access controller (MAC) and PHY Mega Core® functions which implement the IEEE 802.3ba 40G and 100G Ethernet Standard
DDR2 SDRAM Controller for UniPHY
pdf
IP Cores
The Altera® DDR2, DDR3, and LPDDR2 SDRAM controllers with UniPHY, QDR II and QDR II+ SRAM controllers with UniPHY, RLDRAM II controller with UniPHY, and RLDRAM 3 PHY-only IP provide low latency, high-performance
DO-DI-PCI64-DK
DO-DI-PCI64-DK
购买
CAD
pdf
IP Cores
PCI64 INTERFACE V3 AND V4
Unknown
DO-DI-PCI64-SK
DO-DI-PCI64-SK
购买
CAD
pdf
IP Cores
PCI64 INTERFACE V3 AND V4
SYN1588
SYN1588
购买
CAD
pdf
IP Cores
CLOCK M IP-CORE

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