SN74LVC125ADTG4

SN74LVC125ADTG4

Texas Instruments

Description:

Buffer/Line Driver 4-CH Non-Inverting 3-ST CMOS 14-Pin SOIC T/R

Country of Origin:

Malaysia

Introduction date:

Jan 1, 1993

Updated:07-NOV-2024

CAD ModelsRef. Designs

Overview

Familiarize yourself with the fundamental general information, properties, and characteristics of the component, along with its compliance with industry standards and regulations.

LifeCyclePremium
EU RoHS Yes
RoHS Version2011/65/EU, 2015/863
EAR99
Automotive No
Supplier Cage Code01295
8542390060
Schedule B8542390060
No
Dose LevelN/R
PPAP No
AEC Qualified No
Category Path
Semiconductor > Standard and Specialty Logic > Specialty Logic > Buffers and Line Drivers

Datasheet

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Datasheet Preview

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Package

The package information for the component gives important details about the product's size, weight, and packaging. This helps engineers determine if the product meets their requirements and expectations.

Basic Package Type
Package Family Name
Supplier Package
Package Description
Lead Shape
Pin Count
PCB
Package Diameter (mm)
Package Weight (g)
Package Material
Mounting
Package Outline
Package Overall Height (mm)
Package Overall Width (mm)
Package Overall Length (mm)
Jedec
Jedec info (PKG outline)

Manufacturing

The manufacturing information specifies the technical requirements and specifications for producing and assembling the component. This information is crucial for manufacturers to maintain the quality and reliability of the components, and ensure they are compatible with other devices and components.

Parametric

The parametric information displays vital features and performance metrics of the component, which helps engineers and supply chain managers to compare and choose the most appropriate electronic component for their applications and needs.

Product Line
Absolute Propagation Delay Time
Maximum Storage Temperature
Typical Quiescent Current
Maximum Quiescent Current
Supplier Temperature Grade
Minimum Test Temperature
Maximum Test Temperature
Maximum Supply Current
Typical Supply Current
Maximum High Level Output Current
Number of Input Enables per Chip
Number of Output Enables per Chip
Number of Channels per Chip
Bus Hold
Maximum Propagation Delay Time @ Maximum CL
Maximum Power Dissipation
Minimum Storage Temperature
Input Signal Type
Propagation Delay Test Condition
Logic Family
Logic Function
Number of Elements per Chip
Number of Inputs per Chip
Number of Outputs per Chip
Polarity
Output Type
Maximum Low Level Output Current
Minimum Operating Supply Voltage
Typical Operating Supply Voltage
Maximum Operating Supply Voltage
Tolerant I/Os
Minimum Operating Temperature
Maximum Operating Temperature
Process Technology

Reference designs

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CAD Models

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Crosses

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