Datasheets
EP1S30F1020C7N

EP1S30F1020C7N

Intel

Description:

FPGA Stratix® Family 32470 Cells 420.17MHz 130nm Technology 1.5V 1020-Pin FC-FBGA

Country of Origin:

Korea (Republic of)

Introduction date:

Sep 6, 2001

Updated:+90 days

See more Field Programmable Gate Arrays - FPGAs by Intel
Part SpecificationsPrice & Availability

Overview

Familiarize yourself with the fundamental general information, properties, and characteristics of the component, along with its compliance with industry standards and regulations.

LifeCyclePremium
EU RoHSYes with Exemption
RoHS Version2011/65/EU, 2015/863
3A001.a.7.a
Automotive No
Supplier Cage Code4BA62
8542310060
Schedule B8542310060
PPAP No
AEC Qualified No
Category Path
Semiconductor > Programmable Devices > Programmable Logic Devices > Field Programmable Gate Arrays - FPGAs

Datasheet

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Manufacturing

The manufacturing information specifies the technical requirements and specifications for producing and assembling the component. This information is crucial for manufacturers to maintain the quality and reliability of the components, and ensure they are compatible with other devices and components.

Reflow Temp. Source
Wave Temp. Source

Parametric

The parametric information displays vital features and performance metrics of the component, which helps engineers and supply chain managers to compare and choose the most appropriate electronic component for their applications and needs.

Product Line
Maximum DSP Block Frequency
Maximum MLAB Capacity
Device PCIe Hard IP Blocks
Number of Regional Clocks
Maximum LVDS Data Rate
Maximum Differential I/O Pairs
Maximum I/O Performance
Maximum Distributed RAM Bits
Digital Control Impedance
Number of I/O Banks
Mega Multiply Accumulates per second
Tolerant Configuration Interface Voltage
Minimum Storage Temperature
Number of Inter Dielectric Layers
Maximum Storage Temperature
Shift Registers
Number of Global Clocks
Copy Protection
Typical Supply Current
Maximum Power Dissipation
Temperature Flag
In-System Programmability
Maximum Internal Frequency
Supplier Temperature Grade
Reprogrammability Support
Tradename
Device Logic Gates
Device Logic Units
I/O Voltage
Typical Power Consumption
Maximum Quiescent Current
JTAG Support
Maximum Supply Current
Family Name
Maximum Number of User I/Os
Number of Registers
RAM Bits
Device Logic Cells
Number of Look-up Table Input
Device System Gates
Ethernet MACs
Minimum Operating Supply Voltage
Number of Multipliers
Processor Blocks
Typical Operating Supply Voltage
Transceiver Blocks
Maximum Operating Supply Voltage
Transceiver Speed
Program Memory Type
Dedicated DSP
PCI Blocks
Device Number of DLLs/PLLs
Total Number of Block RAM
Maximum Propagation Delay Time
Giga Multiply Accumulates per Second
Maximum Number of SERDES Channels
Speed Grade
Differential I/O Standards Supported
Single-Ended I/O Standards Supported
External Memory Interface
Supported IP Core
Supported IP Core Manufacture
Minimum Operating Temperature
Maximum Operating Temperature
Programmability
Process Technology

Crosses

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