74HCT75N

74HCT75N

Nexperia

Description:

Latch Transparent 4-CH D-Type 16-Pin PDIP

Introduction date:

Sep 19, 1997

Updated:+90 days

Overview

Familiarize yourself with the fundamental general information, properties, and characteristics of the component, along with its compliance with industry standards and regulations.

LifeCyclePremium
EU RoHS Unknown
RoHS Version2011/65/EU
Category Path
Semiconductor > Standard and Specialty Logic > Standard Logic > Latches

Datasheet

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Datasheet Preview

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Parametric

The parametric information displays vital features and performance metrics of the component, which helps engineers and supply chain managers to compare and choose the most appropriate electronic component for their applications and needs.

Product Line
Typical Supply Current
Absolute Propagation Delay Time
Number of Input Enables per Element
Number of Output Enables per Element
Set/Reset
Number of Channels per Chip
Number of Selection Inputs per Element
Propagation Delay Test Condition
Maximum Low Level Output Current
Typical Quiescent Current
Maximum Supply Current
Supplier Temperature Grade
Maximum Propagation Delay Time @ Maximum CL
Bus Hold
Maximum High Level Output Current
Maximum Quiescent Current
Minimum Storage Temperature
Maximum Storage Temperature
Logic Family
Process Technology
Latch Mode
Type
Number of Elements per Chip
Number of Inputs per Chip
Number of Outputs per Chip
Output Type
Polarity
Minimum Operating Supply Voltage
Tolerant I/Os
Typical Operating Supply Voltage
Minimum Operating Temperature
Maximum Operating Supply Voltage
Maximum Operating Temperature

Crosses

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