AD9524/PCBZ, Evaluation Board for Evaluating the AD9524 Clock Generator

AD9524/PCBZ, Evaluation Board for the AD9524 is designed to operate in the same manner. The AD9524 is defined to support the clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive phase noise requirements necessary for acceptable data converter SNR performance. The input receivers, oscillator and zero delay receiver provide both single-ended and differential operation. When connected to a 30.72 MHz to 122.88 MHz reference clock and a VCXO of either 30.72 MHz to 122.88 MHz, the device generates low noise outputs from a range of 0.96 MHz to 983.04 MHz