TIDEP0070, DDR ECC Reference Design to Improve Memory Reliability in 66AK2G02-based Systems

TIDEP0070, Reference Design describes system considerations for Dual Data Rate (DDR) memory interface with Error Correcting Code (ECC) support in high-reliability applications, based on the 66AK2G02 Multicore DSP + ARM processor System-on-Chip (SoC). It enables developers to implement a high reliability based solution rapidly by discussing system interfaces, board hardware, software, throughput performance and diagnostic procedures