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64-bit PCI Bus Master/Target Interface
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CAD
IP Cores
64-bit PCI Bus Master/Target Interface IP Core
Unknown
10 Gigabit Fibre Channel FC-1 Core
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CAD
IP Cores
10 Gigabit Fiber Channel FC-1 Core IP Core
Unknown
IP Cores
10 Gigabit Ethernet Physical Coding Sublayer IP Core
Unknown
40-80 Gbps Transport Switch (TPX4004)
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CAD
IP Cores
40-80 Gbps Transport Switch (TPX4004) IP Core
Unknown
2.5G PDH/SONET/SDH Packet Mapper (TPW48)
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CAD
IP Cores
2.5G PDH/SONET/SDH Packet Mapper (TPW48) IP Core
Unknown
EF-DI-POSL3PHY-SITE
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CAD
IP Cores
The Xilinx® SPI-3 Physical (PHY) Layer core provides a fully compliant Packet over SONET (POS) solution and which can be quickly integrated into networking systems
RIO22000-8-ILT
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CAD
IP Cores
QPRO EXTENDED TEMPERATURE PLATFORM FLASH IN SYSTEM PROGRAMMABLE CONFIGURATION PROM
No
100 Gbps Ethernet MAC
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CAD
IP Cores
40- and 100-Gbps Ethernet (40GbE and 100GbE) media access controller (MAC) and PHY Mega Core® functions which implement the IEEE 802.3ba 40G and 100G Ethernet Standard
10GBase-R PHY
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CAD
IP Cores
The protocol-specific transceiver PHYs configure the PCS to implement a specific protocol. In contrast, the native PHYs provide broad access to the low-level hardware, allowing you to configure many PCS and other functions
40-Gbps Ethernet MAC
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CAD
IP Cores
40- and 100-Gbps Ethernet (40GbE and 100GbE) media access controller (MAC) and PHY Mega Core® functions which implement the IEEE 802.3ba 40G and 100G Ethernet Standard
DDR2 SDRAM Controller for UniPHY
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CAD
IP Cores
The Altera® DDR2, DDR3, and LPDDR2 SDRAM controllers with UniPHY, QDR II and QDR II+ SRAM controllers with UniPHY, RLDRAM II controller with UniPHY, and RLDRAM 3 PHY-only IP provide low latency, high-performance
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