QL3006-4PL68I
QuickLogic描述: | FPGA pASIC 3 Family 8.008K Gates 160 Cells 416.67MHz 0.35um Technology 3.3V 68-Pin PLCC |
推出日期: | Apr 10, 2002 |
更新:21-NOV-2024 | |
線上版本:https://www.datasheets.com/zh-tw/part-details/ql3006-4pl68i-quicklogic-17406801
概述
熟悉元件的基本一般資訊、特性和特點，以及其符合產業標準和法規的情況。
生命週期高級
歐盟RoHS No
RoHS版本2011/65/EU, 2015/863
類別路徑
Semiconductor > Programmable Devices > Programmable Logic Devices > Field Programmable Gate Arrays - FPGAs
Semiconductor > Programmable Devices > Programmable Logic Devices > Field Programmable Gate Arrays - FPGAs
數據手冊
透過下載元件的規格表來全面了解電子元件。這份 PDF 文件包含了所有必要的詳細資訊，如產品概述、特點、規格、評級、圖表、應用等等。
數據表預覽
(Latest 版本)製造
製造資訊指定了生產和組裝元件的技術要求和規格。這些資訊對於製造商來說非常重要，以維護元件的品質和可靠性，並確保它們與其他設備和元件兼容。
參數
參數資訊顯示了元件的重要特性和性能指標，這有助於工程師和供應鏈經理比較和選擇最適合他們應用和需求的電子元件。
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生產線
Maximum DSP Block Frequency
Maximum MLAB Capacity
Device PCIe Hard IP Blocks
Number of Regional Clocks
Maximum LVDS Data Rate
Maximum Differential I/O Pairs
Maximum I/O Performance
Maximum Distributed RAM Bits
Digital Control Impedance
Number of I/O Banks
Mega Multiply Accumulates per second
Tolerant Configuration Interface Voltage
Minimum Storage Temperature
Number of Inter Dielectric Layers
Maximum Storage Temperature
Shift Registers
Number of Global Clocks
Copy Protection
Typical Supply Current
Maximum Power Dissipation
Temperature Flag
In-System Programmability
Maximum Internal Frequency
Supplier Temperature Grade
Reprogrammability Support
Tradename
Device Logic Gates
Device Logic Units
I/O Voltage
Typical Power Consumption
Maximum Quiescent Current
JTAG Support
Maximum Supply Current
Family Name
Maximum Number of User I/Os
Number of Registers
RAM Bits
Device Logic Cells
Number of Look-up Table Input
Device System Gates
Ethernet MACs
Minimum Operating Supply Voltage
Number of Multipliers
Processor Blocks
Typical Operating Supply Voltage
Transceiver Blocks
Maximum Operating Supply Voltage
Transceiver Speed
Program Memory Type
Dedicated DSP
PCI Blocks
Device Number of DLLs/PLLs
Total Number of Block RAM
Maximum Propagation Delay Time
Giga Multiply Accumulates per Second
Maximum Number of SERDES Channels
Speed Grade
Differential I/O Standards Supported
Single-Ended I/O Standards Supported
External Memory Interface
Supported IP Core
Supported IP Core Manufacture
Minimum Operating Temperature
Maximum Operating Temperature
Programmability
Process Technology
