14-Bit, 125 MSPS Quad ADC with SNR Enhanced by Post Digital Summation

Circuit is a simplified diagram of a 14-bit, 125 MSPS quad ADC system that uses post digital summation to increase the signal-to-noise ratio (SNR) from 74 dBFS for a single ADC to 78.5 dBFS for the quad ADC with summation. This technique is especially suitable for applications requiring high SNR such as ultrasound and radar and makes use of modern high performance low power quad pipelined ADCs