Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using the ADF4002 PLL

CN-0003, Application circuit utilizes the ADF4002 frequency synthesizer to generate a very low jitter encode (sampling) clock to control sampling on the AD9215 analog-to-digital converter. Jitter on the encode clock produces degradation in the overall signal-tonoise ratio (SNR). The ADF4002 consists of a low noise digital phase frequency detector (PFD), precision charge pump, programmable reference divider, and programmable N divider. The 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO)