UDPSDR-HF2, 100kHz - 55MHz Receiver Front-End Development Board features the LTC2208 16-bit, 122.88Msps ADC
참조 설계 작성자: Zephyr Engineering, Inc
UDPSDR-HF2, Receiver Development Board features the LTC2208 16-bit ADC sampling at 122.88Msps. The HF2 is designed to be a front-end companion to the Intel® FPGA BeMicroSDK from Arrow Electronics. Together, the HF2 and BeMicroSDK form a complete high-performance 100kHz to 55MHz Digital Down Conversion receiver. The high-performance UDPSDR-HF2 joins the UDPSDR-HF1 (14-bits@80Msps) receiver and the UDPSDR-TX2 transmitter (14-bits@210Msps) to round out the SDRstick family
