TIDEP0033, SPI Master with Signal Path Delay Compensation Reference Design
Conception de référence par: Texas Instruments
TIDEP0033, SPI Master with Signal Path Delay Compensation Reference Design. The Programmable Real-time unit within the Industrial Communication Subsystem (PRU-ICSS) enables customers to support real-time critical applications without using FPGAs, CPLDs or ASICs. This TI design describes the implementation of the SPI master protocol with signal path delay compensation on PRU-ICSS. It supports the 32-bit communication protocol of ADS8688 with a SPI clock frequency of up to 16.7MHz
