I2C Bus Master Reference Design for Lattice CPLD/FPGA devices

I2C Bus Master Reference Design is intended to demonstrate how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in the CPLD/FPGA device. With the flexibility that this I2C-Bus Master Controller offers, a designer can communicate with up to 128 different I2C slave devices operating in standard or fast mode with transactions ranging from 1 to 256 bytes. The user can also customize the VHDL code to meet their own specific requirements and thus reduce valuable CPLD/FPGA area while maintaining the speed performance. This design conforms to the Philips I2C Bus Specification version 1.0